The present invention relates to the field of echo cancellers, and in particular to an echo canceller having a discrete time adaptive filter having a reduced number of non-zero filter tap weights.
As known, bothersome echoes occur in communication systems, such as telephone systems, that operate over long distances or in systems that employ long processing delays, such as digital cellular systems. The echoes are the result of electric leakage in the four-to-two/two-to-four wire hybrid circuit, due to an impedance mismatch in the hybrid circuit between the local loop wire and the balance network. To reduce the echoes, communication systems typically include one or more echo cancellers.
FIG. 1 is a block diagram illustration of a communication system 10 that connects at least two subscribers 12, 14. The first subscriber 12 is typically connected to the communication system 10 via a two-wire line 16 and a hybrid circuit 18. The hybrid circuit 18 connects the two-wire line 16 to the four-wire lines 20, 22. The first four-wire line 20 provides a signal to the second subscriber via a second hybrid circuit 24 and a two-wire line 26. Similarly, signals from the second subscriber 14 are routed to the first subscriber 12 over the two-wire line 26, the second hybrid circuit 24 and the four-wire line 20, 22. In one application, the hybrid circuits may be located in the telephone company central offices. To reduce the echo signals coupled by the hybrid circuit due to impedance mismatches, echo cancellers 30, 32 are included to attenuate the undesirable echoes.
Echo cancellers typically include an adaptive filter that generates an estimate of the echo and subtracts the estimate from the return signal. Like any adaptive discrete time filter, the tap weights of the filter are adjusted based upon the difference between the estimate of the echo signal and the return signal. The adaptive filter employs an adaptive control routine to adjust the tap weights in order to drive the value of the difference signal to zero or a minimum value.
A problem with prior art echo cancellers is that they are required to handle echo tail lengths of up to 128 milliseconds per industry standard ITU G. 168. However, in order to meet this requirement the adaptive filter would have to have 1024 taps. Of course providing a filter having such a large number of taps leads to a relatively large computational burden associated with the echo cancellers. In a digital signal processor embodiment (DSP), such an echo canceller would require a relatively large percentage of the DSP's available processing power (e.g., MIPS). For example, using an LMS algorithm with such a large number of tap weights requires a significant amount of processing power (e.g., 24 MIPs). Similarly, if the 1024 tap adaptive filter is implemented in an application specific integrated circuit (ASIC), a large number of gates would be required.
Therefore, there is a need for an echo canceller that employs a computationally efficient adaptive filter for calculating the estimated echo signal.